Complementary Metal Oxide Semiconductor (CMOS) devices are widely used to form integrated circuits and sensors. Historically one of the principal problems to be overcome was the development of surface passivation techniques to reduce the number of surface states for electrons at the silicon oxide interface. These surface states resulted in variations in the threshold voltage and large values of low frequency or 1/f noise. N-channel transistors, where the carriers in the surface channel of the transistor are electrons, were particularly problematic and always had more low frequency noise than p-channel devices. Surface passivation techniques were developed and micrometer, μm, size transistors, where the conduction can be considered to be a sheet of charge, gained wide acceptance. The terms micrometer size, or micrometer scale, devices refers to transistors in which the length and width of a top view of the conduction channel has dimensions of micrometers, μm. Sub-micron devices have dimensions less than micrometers, or dimensions of nanometers, nm. In nanometer dimension, or nanoscale devices, however, as device dimensions begin to approach atomic dimensions, size effects become important and the location of individual electronic charges in the devices become important. This is particularly important in CMOS image sensors that can be used to detect only a few photoelectrons. MOS or CMOS image sensors are widely used in digital cameras and cell phone cameras.
The use of transistors with lower threshold voltages is known to improve the output voltage swing and the overdrive, VGS-VT, of MOS transistors. Improving the overdrive, VGS (gate to source voltage)−VT (turn-on or threshold voltage), improves the speed and the performance of MOS transistors in either analog or digital integrated circuits. In particular some techniques for fabricating lower threshold transistors and improving the output voltage swing range have been described for image sensors and their applications.
Image Sensors
Chao Shen; Chen Xu; Weiquan; Huang, W. R.; Mansun Chan; “Low voltage CMOS active pixel sensor design methodology with device scaling considerations,” Proceedings Electron Devices Meeting, IEEE Hong Kong 30 Jun. 2001, pp. 21-24 describes how higher threshold voltage transistors impose significant limitations on CMOS APS imagers. This is shown in FIG. 1a, where the available input swing is only VDD−2 VT−VDS M4. The pixel shown in, 101, is known as a 3T or three transistor pixel, where M1, M2 and M3 are the three transistors of the pixel and M4 is the sense transistor and is common to many pixels. The photodiode 115 is arranged as shown. VDD is the positive DC power supply voltage and 107 shows the effective input voltages to transistor M2 and output voltage or voltage at the source of transistor M2. The effective input to the voltage of transistor M2 is shown in 105, the input voltage to M2 cannot rise higher than VDD minus the threshold or turn on voltage of M1, VTM1. If the input voltage to transistor M2 falls below the threshold voltage of transistor M2, VTM2, plus the drain to source voltage of transistor M4, VDSM4, then transistor M2 cannot turn on. The output voltages are shown in 106 where the output voltage cannot be higher than VDD minus the threshold voltage of transistor M1, VTM1, minus the threshold voltage of transistor M2, VTM2. The output voltage cannot fall below the drain to source voltage of transistor M4,VDSM4. This arrangement significantly limits the dynamic range of a CMOS active pixel sensor (APS) output in an imager pixel circuit as shown in FIG. 1a. Similar considerations however apply to the more commonly employed 4T pixel arrangement 110 shown in FIG. 1b, which employs an added transistor as a transfer device 112. U.S. Pat. No. 7,214,575 describes techniques for making some transistors with lower threshold voltages or a transistor of a pixel cell for use in a CMOS imager with a lower threshold voltage and multiple VT transistors as part of active pixel cells of a CMOS imager or a CCD imager. A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V was disclosed. The transistor is provided with conventional high dosage source and drain regions around the gate electrode and with conventional halo implanted regions around the drain to prevent punch through. The conventional lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V. Min-Hwa Chi describes “Technologies for high performance CMOS active pixel imaging system-on-a-chip,” in the Proceedings 5th International Conference, 21-23 Oct. 1998, pp. 180-183. Low VT or depletion mode transistors are needed in the pixel transistors and column sense amplifier, for a larger range of voltage in analog circuits. None of these however describe or propose the use of lower threshold voltage, VT, transistors for reduced noise.
The trapping and release of electrons in the gate insulator of MOS devices can result in changes in the threshold voltage and drain current of conventional micrometer size transistors. These changes result in RTS or 1/f noise in the transistor. These changes in drain current are described by a conventional model for micrometer scale devices, where there is a uniform sheet of charge and average change in the overall threshold voltage. For instance for a 0.35 μm by 0.35 μm transistor where the gate oxide is 66 Å, or 6.6 nm, thick, the fluctuation of a single electronic charge would contribute about 0.3 mV to the threshold voltage and the average change in drain current would be only about 0.03%. These values are much smaller than those predicted by the atomistic model, described later, for sub-nanometer dimension transistors. RTS and 1/f noise become significant problems in nanometer dimension devices of sizes 1000 nm or less. In image sensors the noise of the source follower is critical in determining the ability to detect the minimal number of photoelectrons stored on the photodiode capacitance.
Sense Amplifiers and Comparators
If there are a large number of trapped electrons in the gate insulator there can, of course, be a simultaneous de-trapping or emission of several electrons at one time or, more importantly as will be shown later, conduction in percolation, or small river-like, channels. The probability that there will be a large change in threshold voltage causing an error has been found to be described by a lognormal distribution as described by Drake A. Miller, Panupat Poocharoen and Leonard Forbes, “1/f noise and RTS (random telegraph signal) errors in sense amplifiers,” IEEE Workshop on Microelectronics and Electron Devices, Boise, Id., 20 Apr. 2007, pp. 22-22. In a lognormal distribution the probability of a large value is of the order exp(−x). The results in L. Forbes, D. A. Miller and P. Poocharoen, “1/f Noise and RTS (Random Telegraph Signal) Errors in Comparators and Sense Amplifiers,” NanoTech, Santa Clara Calif., 2007, vol. 1 pp. 197-200 show a 0.1% probability of a value twenty times the minimal RTS step of 10 mV on a minimum size device in a 90 nm technology with 9 nm gate oxides. This would be 200 mV, corresponding to an apparent fifty traps changing charge state. In reality the large change in drain current is not due to fifty traps changing charge state but rather modulation of conduction in percolation channels as described later in our model for nanometer dimension transistors or transistors with sub-micron dimensions. For a sense amplifier in 50 nm technology with 2 nm gate oxides and a transistor width to length size of W/L=2.5 μm/0.5 μm, this translates into a threshold voltage distribution. If a DRAM sense amplifier is upset by such a threshold voltage mismatch of ΔVT=200 mV, then the error rate can be calculated.
Nanoscale Memory Circuits
L. Forbes, D. A. Miller and M. Y. Louie, “1/f Noise and RTS (Random Telegraph Signals) and Read Errors in Nanoscale Memories,” NanoTech, Santa Clara Calif., 2007, vol. 1, pp. 156-159 describes the problem of detecting the small number of electrons stored in nanoscale memories. The minimum number of electrons that can be detected is limited or increases with (a) the magnitude of the 1/f noise and (b) as the lower bandwidth decreases or time differences between read signals increases. This determines the minimum number of electrons in a single memory element that can be detected. If one electron is stored, ΔNt=1, then the time until there is an error can be calculated as the time to failure, tf, where tf is determined by the lower bandwidth. ΔNt=1 describes the single electron being stored, or number of electrons being stored. For a single memory element or cell this can be a very long time. Practical memories, however, have a very large number of individual elements or bits, N, typically a gigabit. N is the number of elements or cells storing electrons. Practical memories require very low bit error rates. If the failure rate is constant, tf is the same for all bits, and if there are N=1G bits then for a nanoscale memory the bit error rate will be around 10−6/sec or there will be many more than one bit error per year, since one year is over 107 seconds. This is higher than the desired rate of one bit error per year. However these error rates are much smaller than those predicted by our model described later for nanometer dimension transistors, or transistors with sub-micron dimensions. RTS and 1/f noise become significant problems in nanometer dimension devices of sizes 1000 nm or less.
Analog Integrated Circuits
Like nanoscale memories, CMOS analog integrated circuits work on the basis of charge store on capacitive nodes. The gain of a switched capacitor amplifier for instance depends on the ratios of two charges, charge is first stored on an input capacitor and then this charge is tranferred to a feedback capacitor. Low frequency or RTS noise will introduce an added uncertainty, or noise, into the output voltage and there will be a significant error in the output voltage. However the noise calculated by conventional models is much smaller than those predicted by the atomistic model for sub-nanometer dimension transistors. RTS and 1/f noise become significant problems in nanometer dimension devices of sizes 100 nm or less. In nanoscale devices this noise can be larger than the normal thermal noise or noise associated with the resistance of the channel. RTS noise is an important limitation in nanoscale analog integrated circuits.
Digital Integrated Circuits
Digital CMOS circuits depend upon one transistor being turned off, for instance the NMOS channel transistor in an inverter while the other complementary transistor, a PMOS, is turned on. This will yield a high voltage or positive logic one signal at the output. In the case of nanoscale transistors there is a finite probability that multiple electrons might be emitted as RTS noise and escape from the gate insulator in the NMOS transistor resulting in sub-threshold conduction as described by Drake A. Miller, Panupat Poocharoen and Leonard Forbes, “Subthreshold leakage due to 1/f noise and RTS (random telegraph signals),” IEEE Workshop on Microelectronics and Electron Devices, Boise, Id., 20 Apr. 2007, pp. 23-24. Such sub-threshold conduction can upset the output voltage in static logic CMOS circuits. In dynamic CMOS integrated circuits sub-threshold conduction is particularly detrimental since it can easily discharge capacitive nodes resulting in logic errors. Again these error rates are much smaller than those predicted by our model described later for nanometer dimension transistors, or sub-micron transitors. RTS and 1/f noise become significant problems in nanometer dimension devices of sizes 1000 nm or less.
Noise
Low-frequency noise in metal-oxide semiconductor devices is generally categorized into two groups: 1/f and random telegraph noise (RTN). In the first case a measurement of the noise results in a noise power spectrum that has a 1/f slope that continues to low frequencies. RTN on the other hand has a different character as compared to 1/f. RTN appears with a Lorentzian-shaped noise spectrum with a low frequency plateau and a roll off of 1/fm with m=2. The fundamental noisemechanism behind the low-frequency noise in metal-oxide-semiconductorstructures is theorized to be the interaction of surface charge with slow traps in the oxide near the interface. These interface traps have a sufficient spread in energy such that the summation of these traps spans many decades of time constants and could account for a 1/f slope spanning many decades of frequency.
Deep levels in semiconductors are capable of causing a fluctuation in the generation, recombination, and trapping rates of charge which results in a fluctuation of the charge density. This fluctuation is detected as a change inconductivity and sensed either as a current or voltage. This type of fluctuation is called Generation-Recombination (GR) noise. This type of noise is found in the channel of IFET's, photoconductors, and semiconductor resistors. For the energy level to act as a GR noise source the characteristic energy must be relatively deep in the band gap of the semiconductor.
RTS noise has a similar power spectrum in most respects to GR noise. RTS has also been named burst or popcorn noise and fundamentally does not differ as to the origin of the noise except that RTS is considered a fundamental phenomenon while burst noise was most often associated with poor device quality. It is pretty well accepted now that the behavior of RTS is due to the capture and emission of traps near a current carrying region where the field set up by the trapped charge causes a change in the local conductivity and/or mobility. RTS has been categorized with 1/f noise since a 1/f spectrum can be generated from the random capture and emission of several fluctuating traps.
P-channel transistors have been observed to have less noise and in comparisons for large devices, for example those devices having a width-to-length, W/L, =100 μm/32 μm. D. C. Murray, J. C. Carter, and A. G. R. Evans, “CMOS 1/f Noise: n-Channel Versus p-Channel,” Appl. Phys. A, vol. 51, pp. 337-339, 1990 noticed that p-channel transistors have less noise than n-channel transistors at comparable drain current. Further, D. C. Murray, J. C. Carter, and A. G. R. Evans, “CMOS 1/f Noise: n-Channel Versus p-Channel,” Appl. Phys. A, vol. 51, pp. 337-339, 1990 observed that counter-doping of p-channel devices by ion implantation would result in a lower noise.
RTS noise in MOS devices has provided an interesting tool for studying the behavior of traps and poses interesting engineering challenges. It is well established now that RTS in MOS devices is the result of the capture and emission of minority charge carriers in the gate oxide of the device. There has been extensive work in modeling and understanding the mechanisms at play. The action and behavior of traps is well understood, so much of the modeling has revolved around understanding the large modulation of the current that is observed in the measurements. In general the behavior or capture and emission rates of traps are taken from considering Shockley-Reed-Hall (SRH) statistics and assuming a tunneling capture mechanism.
One of several approaches taken to model the RTS amplitudes is the model assuming a cored-out area of low conductivity due to the trapped charge reduces the carrier number in the channel by an amount equal to this reduced device area. In this approach the field setup by the trapped charge creates an exclusion zone depending on the depth of the trap into the oxide and the level of inversion charge in the channel. This exclusion zone causes the conduction current to flow in small separated river like or percolation channels rather than a sheet of charge. Variations in potential near the source terminal of the transistor have been described byG. Slavcheva et al., “Potential Fluctuations in metal-oxide-semiconductor field-effect transistors generated by randomly distributed impurities in the depletion layer,” J. Appl. Phys., vol. 91, no. 7, pp. 4326-4324, 2002; L. Forbes, D. A. Miller and M. Y. Louie, “Single Election Trapping in Nanoscale Transistors; RTS (Random Telegraph Signals) and 1/f Noise,” NanoTech, Santa Clara Calif., 2007, vol. 4, pp. 569-562; and L. Forbes and D. A. Miller, “A percolation model for Random Telegraph Signals in Metal-Oxide-Silicon Field Effect Transistor drain current and threshold voltage distributions,” Appl. Phys. Lett., vol. 93, no. 4, pp. 043517-1-3, 28 Jul. 2008.
Phase Noise in RF and Microwave Circuits
It is well known that low frequency 1/f noise (or equivalently RTS noise) results in phase noise in RF, radio frequency, and microwave circuits and specifically CMOS RF circuits. Phase noise in a CMOS voltage controlled oscillator, VCO, results in not a single frequency but a broad band of frequencies. This results in inefficient use of the radio frequency spectrum since a single signal now occupies a band of frequencies not a single frequency.
Effect of RTS and Low Frequency Noise on Integrated Circuits
Models that describe the conduction of electrons in percolation channels have been described by D. A. Miller, M. E. Jacob, L. Forbes, “Compact Model of Low—Frequency Noise in Nanoscale Metal-Oxide-Semiconductor Field Effect Transistors,” Technical Proceedings of the Nanotechnology Conference and Trade Show, vol. 3, Workshop on Compact Modeling, pp. 632-635, 2009, and L. Forbes and D. A. Miller, “Characterization of Single Electron Effects in Nanoscale MOSFET's,” Proc. SPIE, vol. 7402, pp. 740201-1 to -8, 2009.
As a result of the aforementioned reasons or as a consequence thereof, there is a need to minimize RTS noise in both analog and digital MOS and CMOS integrated circuits and RF circuits. A model that utilizes the concept of a uniform sheet of charge in the channel of a MOSFET, such as conventionally used for micrometer, or micron, devices, does not predict the noise performance of nanoscale devices well. In that the prediction cannot adequately reflect the noise performance seen in practice for very small devices, improvements in performance are not easily envisioned. Accordingly, an improvement in the noise model of MOSFET devices can lead to structure changes in construction and operation of such devices. This becomes more important as device dimensions decrease and with the application of nanoscale dimension devices.